The present invention relates generally to computer processing systems, and more specifically, to target buffer address region tracking.
An instruction pipeline in a computer processor improves instruction execution throughput by processing instructions using a number of pipeline stages, where multiple stages can act on different instructions of an instruction stream in parallel. A conditional branch instruction in an instruction stream may result in a pipeline stall if the processor waits until the conditional branch instruction is resolved in an execution stage in the pipeline before fetching a next instruction in an instruction fetching stage for the pipeline. A branch predictor may attempt to guess whether a conditional branch will be taken or not. Branch target prediction attempts to guess a target of a taken conditional or unconditional branch before it is computed by decoding and executing the instruction itself. A branch target may be a computed address based on an offset and/or an indirect reference through a register.
A branch target buffer (BTB) is used to predict the target of a predicted taken branch instruction based on the address of the branch instruction. Predicting the target of the branch instruction can prevent pipeline stalls by not waiting for the branch instruction to reach the execution stage of the pipeline to compute the branch target address. By performing branch target prediction, the branch's target instruction decode may be performed in the same cycle or the cycle after the branch instruction instead of having multiple bubble/empty cycles between the branch instruction and the target of the predicted taken branch instruction.